The present disclosure relates to a solid-state imaging device, a manufacturing method thereof, and an electronic apparatus, such as a camera, including a solid-state imaging device.
As a solid-state imaging device (image sensor), a CMOS solid-state imaging device has been widely spread. The CMOS solid-state imaging device is used, for example, for various personal digital assistances, such as a digital still camera, a digital video camera, and a mobile phone having a camera function.
The CMOS solid-state imaging device is formed of a plurality of pixels arranged in a two-dimensional matrix, each pixel unit having a photodiode which functions as a light receiving portion and a plurality of pixel transistors. The number of the pixel transistors is generally four, a transfer transistor, an amplification transistor, a reset transistor, and a selection transistor, or is three out of the above four other than the selection transistor. Alternatively, these pixel transistors may be shared by a plurality of photodiodes. In order to read out a signal current by applying a desired pulse voltage to these pixel transistors, terminals of the pixel transistors are connected through multilayer wires.
In a backside illuminated solid-state imaging device, a multilayer wiring layer containing layers of wires with at least one interlayer insulating film provided therebetween is disposed on a surface of a semiconductor substrate in which photodiodes and pixel transistors are formed, a support substrate is adhered to a multilayer wiring layer side, and the thickness of the semiconductor substrate is subsequently reduced. That is, the semiconductor substrate is polished from a rear surface side thereof to obtain a desired thickness. Next, a color filter and an on-chip lens are formed on a polished surface, so that a backside illuminated solid-state imaging device is formed.
In the backside illuminated solid-state imaging device, since the structure is formed so that light is incident on a photodiode from a rear surface side of the substrate, the numerical aperture is increased, and a solid-state imaging device having high sensitivity is realized.
In addition, in the solid-state imaging device, as an element isolation region for isolating pixels from each other, for example, there may be mentioned an element isolation region by an impurity diffusion layer, an element isolation region by a trench structure, or an element isolation region by a selective oxidation (local oxidation of silicon, LOCOS) layer. The impurity diffusion layer and the trench structure are suitably used for a microfabrication process as compared to the selective oxidation layer.
As documents relating to the CMOS solid-state imaging device, for example, Japanese Unexamined Patent Application Publication Nos. 2003-31785, 2005-302909, 2005-353955, and 2007-258684 may be mentioned. Japanese Unexamined Patent Application Publication No. 2003-31785 has disclosed a basic structure of a backside illuminated CMOS solid-state imaging device in which wires are formed at one surface side of a semiconductor substrate in which photodiodes are formed and in which visible light is allowed to be incident on the other surface side. Japanese Unexamined Patent Application Publication No. 2005-302909 has disclosed a shallow trench isolation (STI) structure used as an element isolation region of a CMOS solid-state imaging device. Japanese Unexamined Patent Application Publication No. 2005-353955 has disclosed the structure in which in a backside illuminated CMOS solid-state imaging device, a light-shielding layer is disposed at a rear surface side. Japanese Unexamined Patent Application Publication No. 2007-258684 has disclosed the structure in which in a backside illuminated CMOS solid-state imaging device, a film having a negative fixed charge is formed on a light receiving surface so as to suppress the generation of dark current at the interface. As the element isolation region of a solid-state imaging device, the structure formed by a trench, the inside of which is maintained hollow, has also been disclosed (see Japanese Unexamined Patent Application Publication No. 2004-228407).